:: Instruction set design

nAvm featuring a MISC oriented instruction set. Referencing Wikipedia:

Minimal Instruction Set Computer (MISC) is a processor architecture with a very small number of basic operations and corresponding opcodes. Such instruction sets are commonly stack based rather than register based to reduce the size of operand specifiers. Such a stack machine architecture is inherently simpler since all instructions operate on the top most stack entries. A result of this is a smaller instruction set, a smaller and faster instruction decode unit, and overall faster operation of individual instructions. The downside is that instructions tend to have more sequential dependencies, reducing instruction-level parallelism . MISC architectures have much in common with the Forth programming language , and the Java Virtual Machine. :: www.wikipedia.org/wiki/Minimal_instruction_set_computer

As Ngaro, the MISC oriented virtual machine for Retroforth 10 proves, the advantages of a MISC style instruction-set design applies also to efficient interpretation in software because the performance of interpreters is mainly dominated by the efficiency of its dispatch routine. A MISC style instruction format limiting the dispatch overhead significant, resulting in very efficient interpretation. Furthermore as the number of operation codes is small, more than one can be bundled to one instruction decreasing the dispatch overhead even more. Finally, addressed though a jump table the whole interpreter can be reduced at best to a load and indirect branch operation resulting in a very high run-time performance.

An efficient instruction dispatch is a dominant factor for effective interpretation but not the only one ! Another important aspects are the orthogonality of the instruction set, its code-size efficiency and implicit bottlenecks such as memory checks or inefficient garbage collection at run time.

Register based vm's have the proven advantage against stack based designs for needing less instructions executing similar code. However, this advantage counterbalanced through instruction bundling where there higher decoding overhead becomes a limiting factor. Concerning the other mentioned factors, the nAvm design takes a radical approach: Its abstraction level is hold as low-level as possible to gain performance. Instead, the generally applicable instruction-set permits the implementation of these features at vm-code level. This offers the flexibility of implementation as needed. In the final result a performance advantage remains over high-level vm's with it's implicit inflexibility.

Register set:

There exist only one direct accessible register - TOS (top of stack register). All arithmetic and logic operations take TOS as source and the first data-stack element as operand storing there result in TOS. An exception of this are all instructions which fetching immediate parameters. For these the following memory location is the source and TOS can be an operand storing the result in TOS ! Branches and subroutine calls affect only the return stack.

Register:	TOS (accumulator)	DS (stack pointer)	RS (stack pointer)	PC (program counter)	CD (condition flag)
Size:	cell sized	cell sized	cell sized	cell sized	8 bit

The condition register (CD) is special: A COND instruction compares TOS and the first data-stack element relative to a given condition code as immediate parameter. The result is either CD = 1 (condition true) or CD = 0.

Memory:

All memory operations performing word-sized ! The nAvm ISA define an flat, linear address space where each memory location is a cell with word-size. This unified address space holds program and data (different to AVM where instruction bundles and there immediate parameters address different memory locations).

Instruction set:

Opcode: 0 - Mnemonic:	STACK effect
Immediate parameters:	DUP=0, DROP=1, SWAP=2,OVER=3,INC=4,DEC=5,IncN=6,DecN=7
Condition:	-
Pairable:	YES

The STACK opcode fetching one immediate parameter: effect and performs a specific stack operation on its value:

0: DUP	DS := DS + 1, (DS) := TOS
1: DROP	TOS := (DS), DS := DS - 1
2: SWAP	X := TOS; TOS := (DS), (DS) := X
3: OVER	X := TOS, TOS := (DS-1), (DS-1) := X
4: INC	TOS := TOS + 1
5 DEC	TOS := TOS - 1
6: IncN	(DS-[PC]) := (DS-[PC]) + 1, PC := PC + 1
7: DecN	(DS-[PC]) := (DS-[PC]) - 1, PC := PC + 1