Digilent Nexys2

This page is meant to bear (or refer to) information related to the Nexys2 board used as the primary implementation platform for the uCPU.

Features

Main features of the board include:

128Mbit Micron M45W8MW16 Cellular RAM pseudo-static DRAM device organized as 8Mbytes x 16bits
128Mbit Intel TE28F128J3D75-110 Strata Flash device organized as 8Mbytes x 16bits
A USB connector for downloading FPGA configuration and -very neat!- power supply
A PS/2 port (tested)
A 10-line VGA port, allowing for up to 256 colors (tested)
A 2-wire RS-232 connection
A highspeed Hirose FX2 connector
Four multi-purpose 6-pin headers
8 LEDs (tested)
A 4-digit 7-segment display (tested)
4 buttons (tested)
8 slide switches (tested)

Ordering

It is a little difficult, but not impossible to buy the Digilent Nexys2 in Germany. I was able to buy one for a cheap EUR114.86 (including UPS delivery) at Trenz electronic; it can be ordered here.

Documentation

For Nexys2 Starter's Tutorial, Reference Manual and Schematics, please refer to the documentation page.

VHDL Pinout Constraint Templates

When programming the FPGA, looking up the pin names/numbers for the numerous I/Os can be tedious. This chapter provides a list of tested I/O locations to copy/paste into your .ucf file.

NET "clk" LOC="B8";             # 50MHz clock

NET "btn<0>" LOC="B18";         # Push-button 0 (rightmost)
NET "btn<1>" LOC="D18";         # Push-button 1
NET "btn<2>" LOC="E18";         # Push-button 2
NET "btn<3>" LOC="H13";         # Push-button 3 (leftmost)

# Slide switches
NET "sw<0>" LOC="G18";          # Slide-switch 0 (rightmost)
NET "sw<1>" LOC="H18";          # Slide-switch 1
NET "sw<2>" LOC="K18";          # Slide-switch 2
NET "sw<3>" LOC="K17";          # Slide-switch 3
NET "sw<4>" LOC="L14";          # Slide-switch 4
NET "sw<5>" LOC="L13";          # Slide-switch 5
NET "sw<6>" LOC="N17";          # Slide-switch 6
NET "sw<7>" LOC="R17";          # Slide-switch 7 (leftmost)

# Seven-Segment-Display
# Anodes are lo-active (0=on, 1=off)
NET "anodes<0>" LOC="F17";      # 7-segment display anode for digit 0 (rightmost)
NET "anodes<1>" LOC="H17";      # 7-segment display anode for digit 1
NET "anodes<2>" LOC="C18";      # 7-segment display anode for digit 2
NET "anodes<3>" LOC="F15";      # 7-segment display anode for digit 3 (leftmost)
# Cathodes are lo-active (0=on, 1=off)
NET "sevseg<0>" LOC="L18";      # 7-segment display cathode for segment 0 (top)
NET "sevseg<1>" LOC="F18";      # 7-segment display cathode for segment 1 (upper right)
NET "sevseg<2>" LOC="D17";      # 7-segment display cathode for segment 2 (lower right)
NET "sevseg<3>" LOC="D16";      # 7-segment display cathode for segment 3 (bottom)
NET "sevseg<4>" LOC="G14";      # 7-segment display cathode for segment 4 (lower left)
NET "sevseg<5>" LOC="J17";      # 7-segment display cathode for segment 5 (upper left)
NET "sevseg<6>" LOC="H14";      # 7-segment display cathode for segment 6 (center)
NET "dp" LOC="C17";             # 7-segment display cathode for digital point

# LEDs are hi-active (0=off, 1=on)
NET "led<0>" LOC="J14";         # LED 0 (rightmost)
NET "led<1>" LOC="J15";         # LED 1
NET "led<2>" LOC="K15";         # LED 2
NET "led<3>" LOC="K14";         # LED 3
NET "led<4>" LOC="E17";         # LED 4
NET "led<5>" LOC="P15";         # LED 5
NET "led<6>" LOC="F4";          # LED 6
NET "led<7>" LOC="R4";          # LED 7 (leftmost)

# PS/2 Connector
NET "ps2clk"  LOC="R12";        # PS/2 clock signal
NET "ps2clk"  CLOCK_DEDICATED_ROUTE = FALSE;
NET "ps2data" LOC="P11";        # PS/2 data

# VGA Connector
NET "r<0>" LOC="R9";            # Red channel, lsb
NET "r<1>" LOC="T8";            # Red channel
NET "r<2>" LOC="R8";            # Red channel, msb
NET "g<0>" LOC="N8";            # Green channel, lsb
NET "g<1>" LOC="P8";            # Green channel
NET "g<2>" LOC="P6";            # Green channel, msb
NET "b<0>" LOC="U5";            # Blue channel. lsb
NET "b<1>" LOC="U4";            # Blue channel, msb
NET "hsync" LOC="T4";           # Horizontal sync  (lo-pulse)
NET "vsync" LOC="U3";           # Vertical sync  (lo-pulse)

# RS-232 Connector
NET "rx" LOC="U6";              # RS-232 RX
NET "tx" LOC="P9";              # RS-232 TX

# RAM
# Address lines
# addr<0>                       # not available  (least significant)
NET "addr<1>" LOC="J1";         # Address line 1
NET "addr<2>" LOC="J2";         # Address line 2
NET "addr<3>" LOC="H4";         # Address line 3
NET "addr<4>" LOC="H1";         # Address line 4
NET "addr<5>" LOC="H2";         # Address line 5
NET "addr<6>" LOC="J5";         # Address line 6
NET "addr<7>" LOC="H3";         # Address line 7
NET "addr<8>" LOC="H6";         # Address line 8
NET "addr<9>" LOC="F1";         # Address line 9
NET "addr<10>" LOC="G3";        # Address line 10
NET "addr<11>" LOC="G6";        # Address line 11
NET "addr<12>" LOC="G5";        # Address line 12
NET "addr<13>" LOC="G4";        # Address line 13
NET "addr<14>" LOC="F2";        # Address line 14
NET "addr<15>" LOC="E1";        # Address line 15
NET "addr<16>" LOC="M5";        # Address line 16
NET "addr<17>" LOC="E2";        # Address line 17
NET "addr<18>" LOC="C2";        # Address line 18
NET "addr<19>" LOC="C1";        # Address line 19
NET "addr<20>" LOC="D2";        # Address line 20
NET "addr<21>" LOC="K3";        # Address line 21
NET "addr<22>" LOC="D1";        # Address line 22
NET "addr<23>" LOC="K6";        # Address line 23 (most significant)
# Data lines
NET "data<0>" LOC="L1";         # Data line 0 (least significant)
NET "data<1>" LOC="L4";         # Data line 1
NET "data<2>" LOC="L6";         # Data line 2
NET "data<3>" LOC="M4";         # Data line 3
NET "data<4>" LOC="N5";         # Data line 4
NET "data<5>" LOC="P1";         # Data line 5
NET "data<6>" LOC="P2";         # Data line 6
NET "data<7>" LOC="R2";         # Data line 7
NET "data<8>" LOC="L3";         # Data line 8
NET "data<9>" LOC="L5";         # Data line 9
NET "data<10>" LOC="M3";        # Data line 10
NET "data<11>" LOC="M6";        # Data line 11
NET "data<12>" LOC="L2";        # Data line 12
NET "data<13>" LOC="N4";        # Data line 13
NET "data<14>" LOC="R3";        # Data line 14
NET "data<15>" LOC="T1";        # Data line 15 (most significant)
# Control lines
NET "oe" LOC="T2";              # Output Enable
NET "we" LOC="N7";              # Write Enable
NET "mt_adv" LOC="J4";          # Address Valid
NET "mt_clk" LOC="H5";          # Clock
NET "mt_ub" LOC="K4";           # Upper Byte
NET "mt_lb" LOC="K5";           # Lower Byte
NET "mt_ce" LOC="R6";           # Chip Enable
NET "mt_cre" LOC="P7";          # Control Register Enable
NET "mt_wait" LOC="F5";         # Wait